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7B80: Difference between revisions
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The companion delaying timebase for use in 4-slot mainframes is the [[7B85]]. The [[7B50A]] is essentially a 7B80 with its fastest calibrated sweep rate limited to 5 ns/div. | The companion delaying timebase for use in 4-slot mainframes is the [[7B85]]. The [[7B50A]] is essentially a 7B80 with its fastest calibrated sweep rate limited to 5 ns/div. | ||
From Tekscope Vol.8 No.1, 1976: | From [[Media:Tekscope 1976 V8 N1.pdf|Tekscope Vol.8 No.1, 1976]]: | ||
<blockquote> | <blockquote> | ||
[[Les Larson]] developed the trigger circuitry and served as Project Manager for the 7B80 and 7B85. | [[Les Larson]] developed the trigger circuitry and served as Project Manager for the 7B80 and 7B85. | ||
The sweeps were designed by [[Bruce Hofer]] and the DVM and related logic by [[Paul Farley]]. Much credit is due [[Art Metz]] for his work on the [[155-0126-00|trigger input IC | |||
The sweeps were designed by [[Bruce Hofer]] and the DVM and related logic by [[Paul Farley]]. | |||
Much credit is due [[Art Metz]] for his work on the [[155-0126-00|trigger input IC]] which includes the peak-to-peak automatic trigger circuitry. | |||
[[Gene Andrews]], Program Manager, provided overall direction for the project. | [[Gene Andrews]], Program Manager, provided overall direction for the project. | ||
</blockquote> | </blockquote> | ||