Signetics 82S107: Difference between revisions
(Created page with "{{Monolithic IC |Manufacturer=Signetics |Model=82S107 |Part_nos= |Description=field-programmable logic array |Used_in=4052;FG5010; }} ("Field Programmable ROM patch" in the manufacturer's literature) with tristate outputs, in a 28 pin DIL package. The device is organized as 48 words by 8 bits, addressed via a 16 bit programmable address comparator. Each word can be assigned a unique address within a 64K range by programming the comparator inputs High, Low, or Don't ca...") |
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|Description=field-programmable logic array | |Description=field-programmable logic array | ||
|Used_in=4052;FG5010; | |Used_in=4052;7854;FG5010; | ||
}} ("Field Programmable ROM patch" in the manufacturer's literature) with tristate outputs, in a 28 pin DIL package. | }} ("Field Programmable ROM patch" in the manufacturer's literature) with tristate outputs, in a 28 pin DIL package. | ||
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A typical use is to accommodate field patches to code delivered in mask ROMs. | A typical use is to accommodate field patches to code delivered in mask ROMs. | ||
On program addresses matching a programmed pattern in the 82S107, the flag output disables the mask ROM and enables replacement code, typically stored in a small EPROM, with lower bits of the address supplied from the 82S07's outputs. | On program addresses matching a programmed pattern in the 82S107, the flag output disables the mask ROM and enables replacement code, typically stored in a small EPROM, with lower bits of the address supplied from the 82S07's outputs. | ||
For example, the FG5010 manual explains: | |||
<blockquote> | |||
Patch EPROM U1640 provides for programming flexibility. When the data in a particular ROM address must be changed, the new data can be programmed into the Patch EPROM and substituted whenever the no-longer-valid address is selected. | |||
[...] | |||
When a ROM address for which the data were modified is detected by the FPLA, its FLAG output becomes low, which disables Address Line Buffer U1312 and Address Decoder U1520 and enables Patch EPROM U1640. | |||
At the same time, the FPLA function outputs (F0 through F7) become active and supply address bits BA3 through BA10, which are normally provided by the Microprocessor via buffer U1312. Address lines BA0, BA1, and BA2 are provided by the Microprocessor as usual. | |||
This arrangement maps in eight-byte blocks of the Patch EPROM data whenever address lines A3 through A15 equal one of the addresses programmed into the FPLA. | |||
</blockquote> | |||
{{Part usage}} | {{Part usage}} | ||
Latest revision as of 01:56, 11 August 2024
The Signetics 82S107 is a field-programmable logic array monolithic integrated circuit ("Field Programmable ROM patch" in the manufacturer's literature) with tristate outputs, in a 28 pin DIL package.
The device is organized as 48 words by 8 bits, addressed via a 16 bit programmable address comparator. Each word can be assigned a unique address within a 64K range by programming the comparator inputs High, Low, or Don't care via True/Complement input buffers. The contents of each word are also programmable, and are enabled to the outputs only when a programmed address is detected, which causes the Flag output to go Low.
A typical use is to accommodate field patches to code delivered in mask ROMs. On program addresses matching a programmed pattern in the 82S107, the flag output disables the mask ROM and enables replacement code, typically stored in a small EPROM, with lower bits of the address supplied from the 82S07's outputs.
For example, the FG5010 manual explains:
Patch EPROM U1640 provides for programming flexibility. When the data in a particular ROM address must be changed, the new data can be programmed into the Patch EPROM and substituted whenever the no-longer-valid address is selected. [...]
When a ROM address for which the data were modified is detected by the FPLA, its FLAG output becomes low, which disables Address Line Buffer U1312 and Address Decoder U1520 and enables Patch EPROM U1640. At the same time, the FPLA function outputs (F0 through F7) become active and supply address bits BA3 through BA10, which are normally provided by the Microprocessor via buffer U1312. Address lines BA0, BA1, and BA2 are provided by the Microprocessor as usual.
This arrangement maps in eight-byte blocks of the Patch EPROM data whenever address lines A3 through A15 equal one of the addresses programmed into the FPLA.
Some instruments using part Signetics 82S107
| Instrument | Manufacturer | Class | Model | Description | Introduced |
|---|---|---|---|---|---|
| 4052 | Tektronix | Computer | 4052 | Graphics-capable desktop microcomputer | 1978 |
| 7854 | Tektronix | Oscilloscope | 7854 | 400 MHz waveform-processing scope | 1980 |
| FG5010 | Tektronix | Plug-in | FG5010 | 20 MHz function generator | 1982 |