308: Difference between revisions
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{{Spec | Data timing | Setup time min. 25 ns, hold time min. 0 ns }} | {{Spec | Data timing | Setup time min. 25 ns, hold time min. 0 ns }} | ||
{{Spec | Memory | 2 × 252 eight-bit words (acquisition + reference) }} | {{Spec | Memory | 2 × 252 eight-bit words (acquisition + reference) }} | ||
{{Spec | Trigger mode | PRE (trigger at memory location 240) or POST (location 13) } | {{Spec | Trigger mode | PRE (trigger at memory location 240) or POST (location 13) }} | ||
{{Spec | Trigger delay | 0-65535 clock periods }} | {{Spec | Trigger delay | 0-65535 clock periods }} | ||
{{Spec | Serial data formats | 5, 6, 7 or 8 bits per character, asynchronous (50, 75, 110, 134.5, 150, 200, 300, 600, 1200, 1900, 2400, 4800 or 9600 bits/s or external up to 9600 bits/s) or synchronous up to 9600 bits/s }} | |||
{{EndSpecs}} | {{EndSpecs}} | ||
Revision as of 09:27, 27 May 2017
The Sony/Tektronix 308 is a portable 8-channel, 20 MHz "data analyzer" (logic analyzer) with parallel timing, parallel state, serial (up to 9600 bps) and signature analysis modes.
The 308 uses two probes, the standard P6451 8-channel + clock data acquisition probe, and the optional 16-channel P6406 word recognizer probe. Both use 012-0747-00 cable harnesses to attach to the data source.
Manuals
- Tektronix 308 Operator's Manual (PDF)
- Service manual / schematics needed
Key Specifications
Parallel inputs | Eight data channels + 1 clock channel (P6451 probe), impedance |
---|---|
Word recognizer inputs | Sixteen TTL inputs (+40/-400 μA max.), max. +15/-1 V |
Serial / signature input | BNC connector, 1 MΩ // 40 pF, max. ±250 V on BNC; used with P6107 probe, 10 MΩ // 13 pF, max. ±500 V |
Qualifier input | BNC connector, 10 kΩ, max. +10/-5 V |
Sampling clock | 50 ns to 200 ms per sample (1-2-5 sequence) or external down to 50 ns |
Data timing | Setup time min. 25 ns, hold time min. 0 ns |
Memory | 2 × 252 eight-bit words (acquisition + reference) |
Trigger mode | PRE (trigger at memory location 240) or POST (location 13) |
Trigger delay | 0-65535 clock periods |
Serial data formats | 5, 6, 7 or 8 bits per character, asynchronous (50, 75, 110, 134.5, 150, 200, 300, 600, 1200, 1900, 2400, 4800 or 9600 bits/s or external up to 9600 bits/s) or synchronous up to 9600 bits/s |