7D01: Difference between revisions

7D01 (view source)

Revision as of 12:10, 21 November 2021

96 bytes added , 21 November 2021

no edit summary

Peter

Bureaucrats, Interface administrators, Suppressors, Administrators

36,345

edits

@@ Line 15: / Line 15: @@
 * [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976 (PDF)]]
 }}
-The '''Tektronix 7D01''' is a 16-channel logic analyzer plug-in for the [[7000-series scopes]].
+The '''Tektronix 7D01''' is a 16-channel logic analyzer plug-in for the [[7000-series scopes]] that takes two [[P6451]] 8+1 channel probes.
-It can be used by itself, or with a [[DF1]] or [[DF2]] display formatter that attaches to the left of the 7D01 through a [[D-sub connector|DD-50 connector]].
-The 7D01 takes two [[P6451]] 8+1 channel probes.  It does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs.  When used without a display formatter, it displays a timing diagram, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).
+The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs.  When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).
-The 7D01 acquired data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
+When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available.
+The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
 A built-in word recognizer can trigger on any combination of the 16 data signals plus an external qualifier input.  The recorgnizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.