Open main menu
Home
Random
Log in
Settings
About TekWiki
Disclaimers
TekWiki
Search
7D01: Difference between revisions
Page
Discussion
Repairs
← Older edit
Newer edit →
7D01
(view source)
Revision as of 12:12, 21 November 2021
112 bytes added
,
21 November 2021
no edit summary
Revision as of 12:10, 21 November 2021
(
view source
)
Peter
(
talk
|
contribs
)
No edit summary
← Older edit
Revision as of 12:12, 21 November 2021
(
view source
)
Peter
(
talk
|
contribs
)
No edit summary
Newer edit →
Line 42:
Line 42:
}}
}}
{{EndSpecs}}
{{EndSpecs}}
==Internals==
The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits.
==Notes==
==Notes==
Peter
Bureaucrats
,
Interface administrators
,
Suppressors
,
Administrators
36,375
edits