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7D02: Difference between revisions
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added info about options
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{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Channels | up to 52 - 28 (optionally 44) synchronous, 8 sync or async (timing option) }} | {{Spec | Channels | up to 52 - 28 (optionally 44) synchronous, 8 sync or async (timing option) }} | ||
{{Spec | Signal Inputs standard 7D02 | | |||
*8 Data | |||
*16 Address | |||
*10 Control | |||
*1 Ext. Trigger }} | |||
{{Spec | Memory | 256 words }} | {{Spec | Memory | 256 words }} | ||
{{Spec | Timing option | 8 channels, 255 word acquisition memory, 255 word glitch memory, 9 bit word recognizer; sampling 5 ms to 20 ns; [[P6451]] logic probe }} | {{Spec | Timing option | 8 channels, 255 word acquisition memory, 255 word glitch memory, 9 bit word recognizer; sampling 5 ms to 20 ns; [[P6451]] logic probe }} | ||
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{{EndSpecs}} | {{EndSpecs}} | ||
:[[Category:Specifications needed]] ''please add'' | :[[Category:Specifications needed]] ''please add'' | ||
==Options== | |||
* Option 01 − Timing Option: provides 8 additional asynchronous channels with sample rates up to 50 MHz using [[P6451]] probe | |||
* Option 03 − Expansion: Adds 8 Data and 8 Address lines to 7D02, required for 16 bit microprocessors. | |||
==Links== | ==Links== | ||
* [[Media:Tekscope 1980 V12 N4.pdf | Tekscope Vol. 12 No. 4, Dec 1980]]: Mike Reiney, ''A User-Programmable Logic Analyzer for Microprocessor Design'' | * [[Media:Tekscope 1980 V12 N4.pdf | Tekscope Vol. 12 No. 4, Dec 1980]]: Mike Reiney, ''A User-Programmable Logic Analyzer for Microprocessor Design'' | ||
* [http://www.barrytech.com/tektronix/tek7000/tek7d02.html 7D02 @ barrytech.com] | * [http://www.barrytech.com/tektronix/tek7000/tek7d02.html 7D02 @ barrytech.com] | ||