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11A52: Difference between revisions
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{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Bandwidth | DC to 600 MHz plus 100 MHz and 20 MHz BWL filters }} | {{Spec | Bandwidth | DC to 600 MHz plus 100 MHz and 20 MHz BWL (Bandwidth Limit) filters }} | ||
{{Spec | Number of Inputs | 2 }} | {{Spec | Number of Inputs | 2 }} | ||
{{Spec | Rise time | 580 ps in 1 GHz mainframe such as the [[11402]], [[11402|11402A]]. [[11403]], [[11403|11403A]], [[DSA600|DSA601A]], or [[DSA600|DSA602A]] }} | {{Spec | Rise time | 580 ps in 1 GHz mainframe such as the [[11402]], [[11402|11402A]]. [[11403]], [[11403|11403A]], [[DSA600|DSA601A]], or [[DSA600|DSA602A]] }} | ||
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==Internals== | ==Internals== | ||
Each input channel has a separate 50 ohm attenuator containing, two X10 attenuators, a skin effect correction network, an AC coupling capacitor, a signal pickoff for the input protection network and a switch selecting the calibrator or signal input. In normal operation the calibrator signal to the attenuator is instead connected to ground. | |||
The 11A52 uses custom Tektronix-made chips including the [[155-0076-00]] (M94 overload detector) and [[M377]] amplifier chip. | |||
The signal output of the attenuator feeds the + input of the [[M377]] amplifier IC through a (blue) 50 ohm transmission line, one per input channel. The cable lengths set a standard delay per plugin. | |||
The M377's − input is connected to the ACVS (Analog Control Voltage System) output. | |||
The (differential) display outputs of the two amplifiers are hard-wired in parallel and drive the mainframe’s 50 Ω per side input impedance. The same is true of the trigger outputs of the two amplifiers. | |||
The version of the M377 used in the 11A52 has a 100 Ω output impedance per side so that two of them in parallel create a source impedance of 50 Ω per side. | |||
Each M377 amplifier's nominal common-mode output voltage is zero whether enabled or not. When not enabled, each M377 differential output is exactly zero by design. This fact is used during calibration by the plugin’s firmware to determine the mainframe’s imbalance and compensate for it during normal operation. | |||
In the 11A52, the digital output of the M94 overload detectors (one per channel) are received by the microprocessor. | In the 11A52, the digital output of the M94 overload detectors (one per channel) are received by the microprocessor. | ||