39,282
edits
DC505A: Difference between revisions
Jump to navigation
Jump to search
m
typo
No edit summary |
m (typo) |
||
| Line 71: | Line 71: | ||
An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements. | An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements. | ||
The | The DC505A uses a mix of ECL and TTL dividers and logic, and a [[Mostek MK5007]] four-decade counter/latch/multiplexer (U700). Unlike the similarly-specified [[7D15]], it employs no Tek made custom ICs. | ||
The first counter decade is implemented as a divide-by-2 ECL flip-flop (U350, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain. | The first counter decade is implemented as a divide-by-2 ECL flip-flop (U350, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain. | ||