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7A42: Difference between revisions
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'''Vertical:''' | '''Vertical:''' | ||
:The 7A42 was specifically designed for logic signals (TTL, ECL, CMOS). It is not a Logic Analyzer however – the signal path and display is analog. | :The 7A42 was specifically designed for logic signals (TTL, ECL, CMOS). It is not a Logic Analyzer however – the signal path and display is analog. | ||
:The input V/ | :The input V/div setting can only be seen in the mainframe's readout, and adapts automatically when a [[BNC connector with readout ring|pin-coded ×10 probe]] is attached. (×100 probes are not supported and are incorrectly recognized as ×10.) | ||
:A fifth trace, "Trigger View", displays the trigger function output or external clock input. | :A fifth trace, "Trigger View", displays the trigger function output or external clock input. | ||
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{{Spec | Bandwidth | 350 MHz in [[7104]], 300 MHz in [[7904]] }} | {{Spec | Bandwidth | 350 MHz in [[7104]], 300 MHz in [[7904]] }} | ||
{{Spec | Deflection | | {{Spec | Deflection | | ||
* 0.1 | * TTL mode: 0.1, 0.2 or 0.5 V/div ; 1, 2 or 5 V/div with ×10 probe | ||
* 20 | * ECL mode: 20, 50 or 100 mV/div ; 0.2, 0.5 or 1 V/div with ×10 probe | ||
* always DC coupled | |||
* always DC coupled }} | }} | ||
{{Spec | Input impedance | 1 MΩ // 15 pF or 50 Ω}} | {{Spec | Input impedance | 1 MΩ // 15 pF or 50 Ω }} | ||
{{Spec | Max. input voltage | | {{Spec | Max. input voltage | | ||
* at 1 MΩ: 25 V (DC+peak AC) below 36 MHz, down to 3 V<sub>AC</sub> at 300 MHz | * at 1 MΩ: 25 V (DC+peak AC) below 36 MHz, down to 3 V<sub>AC</sub> at 300 MHz | ||
* at 50 Ω: 5 V<sub>RMS</sub> during any 1 ms interval}} | * at 50 Ω: 5 V<sub>RMS</sub> during any 1 ms interval}} | ||
{{Spec | Trigger level | | {{Spec | Trigger level | | ||
* −1.27 to +1.28 V | * TTL Mode ×1: −1.27 to +1.28 V in 10 mV steps (Preset: 0.14 V) | ||
* −0.254 V to +0.256 V (ECL | * TTL Mode ×10: −12.7 to +12.8 V in 100 mV steps (Preset: 1.4 V) | ||
{{Spec | Hysteresis | 40 mV (TTL), 8 mV (ECL | * ECL Mode ×1: −0.254 V to +0.256 V in 2 mV steps (Preset: –0.13 V) | ||
* ECL Mode ×10: −2.54 V to +2.56 V in 2 mV steps (Preset: –1.3 V) | |||
}} | |||
{{Spec | Trigger Hysteresis | 40/400 mV (TTL), 8/80 mV (ECL) }} | |||
{{Spec | Features | | {{Spec | Features | | ||
* NiCd battery to preserve front-panel control status}} | * NiCd battery to preserve front-panel control status}} | ||