DF1: Difference between revisions
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Tek df1 right internal3.jpg | Tek df1 right internal3.jpg | ||
Tek 7d01 and df1 in 7313.jpg|[[7D01]] and DF1 in [[7313]] | Tek 7d01 and df1 in 7313.jpg|[[7D01]] and DF1 in [[7313]] | ||
Tek_7D01-DF01_timing.jpg | 7D01 + [[DF1]] (or [[DF2]]) Timing Diagram | |||
Tek_7D01-DF01_table.jpg | 7D01 + [[DF1]] (or [[DF2]]) State Table | |||
</gallery> | </gallery> | ||
Revision as of 02:17, 10 January 2022
The Tektronix DF1 is a display formatter for use with the 7D01 logic analyzer. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared. The DF2 is essentially a DF1 with an extra key ("Menu") and additional ROM supporting GPIB diagnostics.
Project manager for the DF1 was Murlan Kaufman.
The DF01 attaches to the 7D01 through a 50-pin D-sub connector on the right side panel only, it has no direct connection to the scope mainframe. The DF1 and 7D01 are mechanically coupled by three nylon standoffs that slide into cutouts in the 7D01's case rails. The bottom two standoffs are fixed and are inserted first, then the connector is plugged in and the third, sliding, stand-off at the top is moved to its locked position.
Key Specifications
Memory | One reference table memory, same as 7D01 capacity (max. 16 channels at 254 bits/ch) |
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Display modes |
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Reset output | Positive 100 μs pulse, ≤0.4 V / ≥2.4 V |
Internals
The DF1 is built around a Motorola 6800 microprocessor with two 2K×8 masked ROMs and sixteen 1K×1 SRAMs (2101).
The 7D01 is often affected by bad TI IC sockets, see the Repairs tab.
Pictures
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Front
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Internal
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Side connector
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Custom ICs used in the DF1
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