3T5: Difference between revisions
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{{Plugin Sidebar | {{Plugin Sidebar | | ||
manufacturer=Tektronix |series=560-series scopes |type= 3T5 | | |||
summary=Programmable Sampling Sweep | | summary=Programmable Sampling Sweep | | ||
image=Tek 3t5 front.jpg | | image=Tek 3t5 front.jpg | | ||
caption=3T5 sweep unit | | caption=3T5 sweep unit | | ||
designers=Murlan Kaufman | | |||
introduced=1969 | | introduced=1969 | | ||
discontinued=(?) | | discontinued=(?) | | ||
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* [[Media:070-0760-00.pdf|Tektronix 3T5 Manual (PDF)]] | * [[Media:070-0760-00.pdf|Tektronix 3T5 Manual (PDF)]] | ||
}} | }} | ||
The '''Tektronix 3T5''' is a remotely programmable [[sampling_oscilloscope|sampling]] sweep, | The '''Tektronix 3T5''' is a remotely programmable [[sampling_oscilloscope|sampling]] sweep, mainly intended for the [[568]] system, but usable on other [[560-series scopes]]. The auto triggering circuit in the 3T5 was designed by [[Murlan Kaufman]]. | ||
mainly intended for the [[568]] system, but usable on other [[560-series scopes]]. | |||
The auto triggering circuit in the 3T5 was designed by [[Murlan Kaufman]]. | |||
It has a digital input that controls a digital timing delay. | It has a digital input that controls a digital timing delay. This allows the window of time that is displayed on the scope to be delayed. | ||
This allows the window of time that is displayed on the scope to be delayed. | |||
The programmable delay is implemented using an internal 10 MHz clock, | The programmable delay is implemented using an internal 10 MHz clock, a counter, and a digital comparator. | ||
a counter, and a digital comparator. | |||
==Specifications== | ==Specifications== |
Revision as of 11:40, 14 August 2021
The Tektronix 3T5 is a remotely programmable sampling sweep, mainly intended for the 568 system, but usable on other 560-series scopes. The auto triggering circuit in the 3T5 was designed by Murlan Kaufman.
It has a digital input that controls a digital timing delay. This allows the window of time that is displayed on the scope to be delayed.
The programmable delay is implemented using an internal 10 MHz clock, a counter, and a digital comparator.
Specifications
please add