The interconnect on either slot type is a 76-pin PCB edge connector. The pinout on vertical and horizontal slots is not identical but
compatible to the point that vertical plugins can be installed in horizontal slots and vice versa. However, in that case, some functions may
be unavailable − for example, trigger signals are only routed to H slots so a timebase in a V slot must be externally triggered.
Looking into the mainframe from the front panel, "A" pins are left of the connector centerline (on the plug-in PCB's component side) and "B" are on the right (on the plugin PCB's solder side). Pins are numbered from 1 at the bottom to 38 on the top.
In the following table, (H) indicates signals available in horizontal slots only, (H-A) is horizontal slot A, (H-B) is horizontal slot B, and (V) denotes signals available in vertical slots only.
IEEE-488 bus used in 7A16P, 7A29P, 7B90P, digitizer mainframes; data 1-8 on TS2-TS9 lines
Description of signals
Sweep Gate − 0/+5 V, high while sweep is running (beam unblanking); +Gate Output on mainframe uses Sweep Gate from H slot A when A Gate is selected, and from H slot B when B is selected
Delay Mode Control − Output on delaying timebase in horizontal slot A, connected to input on delayed timebase in horizontal slot B. >+3 V disables auto sweep in delayed timebase; 0 V enables independent timebase function.
A/B Sweep − 500 mVp-p, negative-going copy of sweep signal from timebase, not affected by X position control or magnifier; Used for mainframe's Sawtooth Out, additionally fed to V plugins
Line Trigger − Approx. 1 VRMS mains-frequency signal from power supply (through transformer)
Trigger Holdoff −
Chop Drive −
Chop Mode Sense −
Aux Sweep Gate −
Alt Drive −
Intensity Limit − Switched to ground by timebase in slow sweep speeds (≥100 ms/Div), limits beam intensity to protect the CRT phosphor
Mainframe Channel Switch −
Sweep Inhibit −
Delay Gate − negative-going pulse starting at the end of the delay period, and lasting until the end of the sweep from the delaying timebase. +Gate Output on mainframe uses Delay Gate from H slot B when Delay Gate is selected.
Single sweep ready − 0/+5 V, high when single sweep is ready
X comp. inhibit − Connected to ground in amplifiers, switched to ground by timebase set to amplifier (X-Y) mode to enable X-Y delay compensation in scopes with that function (7904 Opt.2, 7104 Opt.2)
Signal − Signal output from plugin to mainframe. Differential, 50 Ω per side. 50 mV/Div (differential).
Trigger − Copy of signal output from V plugin to mainframe. Differential, 50 Ω per side. 50 mV/Div (differential). Terminated on H slots.
Aux Y-Axis − Current-driven input to mainframe allowing vertical separation of two traces with dual timebase plugins.
Dual Beam Aux Y-Axis −
Single Sweep Logic −
Single Sweep Reset − Switched to ground to reset single sweep.
Mainframe Mode −
Aux Z Axis − Current-driven input to mainframe allowing plugins to modulate beam intensity, e.g. in dual timebase A intensified by B display mode.
Trigger In − Trigger signal input on H plugin, routed from V plugin's trigger output. Differential, 50 Ω per side.
Aux Trigger In −
GPIB lines − Control signal functions are the same as their IEEE-488 (GPIB) equivalents. Time slot lines 2 to 9 double as IEEE-488 data lines.
TS1−TS10 − readout system time slot pulses. Idle 0, active −15 V.
Force Readout −
Plugin Mode −
Ch1/2 Row/Col − Analog current inputs to the readout system. Ch1 refers to the first channel within the plugin slot in question and is associated with the readout field on top of the screen. Ch2 is the 2nd channel displayed at the bottom. Row/Current signals accept negative currents in 100 μA steps; typically, plugins contain resistors from time slot signal lines to row/current lines.
Notes
[note 1] Output from H plugins, input on V plugins
[note 2] Output from V plugins, unused and terminated 50 Ω to ground in mainframe H slots
[note 3] In programmable mainframes, A24 is pulled high to +3 V, indicating to programmable plug-ins to use TS2-TS9 as GPIB lines and a modified readout logic using only TS1 and TS10, with TS1 being active in time slot 1 as in other mainframes, and TS10 being active in each time slot.
[note 4] Not provided by most mainframes (digitizers only?). 7A16P connects B27 to A9, requires −5.2 V on A27.
