Tektronix 7000 series oscilloscope mainframes have one (7912) or two vertical plug-in slots, and zero (7612D), one (7xx3, 7912) or two (7xx4) horizontal plug-in slots.
According to Barrie Gilbert in The Gears of Genius, the 7000 series backplane was largely developed by Les Larson.
The interconnect on either slot type is a 76-pin, 0.1" pitch PCB edge connector. The pinout on vertical and horizontal slots is not identical but
compatible to the point that vertical plugins can be installed in horizontal slots and vice versa. However, in that case, some functions may
be unavailable − for example, trigger signals are only routed to H slots so a timebase in a V slot must be externally triggered.
Looking into the mainframe from the front panel, "A" pins are left of the connector centerline (on the plug-in PCB's component side) and "B" are on the right (on the plug-in PCB's solder side). Pins are numbered from 1 at the bottom to 38 on the top.
In the following table, (H) indicates signals available in horizontal slots only, (H-A) is horizontal slot A, (H-B) is horizontal slot B, and (V) denotes signals available in vertical slots only.
||Sweep Gate (H)
||Delay mode ctl in (H-B)
||Delay mode ctl out (H-A)
||A Sweep (V & H-A) [note 1]
||B Sweep (V & H-B) [note 1]
||Trigger holdoff (H)
||Aux Swp gate (H)
||Intensity Limit (H)
||MF Channel Switch
||Sweep inhibit (H)
||+5 V (lights)
||Delay gate (H)
||Single sweep ready (H)
||X comp inhibit (H)
||+Trigger (V) [note 2]
||−Trigger (V) [note 2]
||Dual beam Aux Y-Axis
||Single sweep logic
||Single sweep reset (H)
||Aux Y axis (H)
||Aux Z axis
||Aux Z common
||+Trigger in (H)
||−Trigger in (H)
||+Aux trigger in (H) [note 5]
||−Aux trigger in (H) [note 5]
||/EOI [note 6]
||/SRQ [note 7]
||/IFC [note 3]
or Inter-plugin GND [note 8]
||−5.2 V [note 4]
or Inter-plugin link
|5.1 V [note 4] |
or Inter-plugin link
||TS10 [note 3]
||TS1 [note 3]
||Plugin mode [note 8]
||Ch. 1 Col
||Ch. 1 Row
||Ch. 2 Col
||Ch. 2 Row
Pin group function legend
Description of signals
- Sweep Gate − 0/+5 V, high while sweep is running (beam unblanking), connected to +5 V in amplifier plugins; +Gate Output on mainframe uses Sweep Gate from H slot A when A Gate is selected, and from H slot B when B is selected.
- Delay Mode Control − Output on delaying timebase in horizontal slot A, connected to input on delayed timebase in horizontal slot B. >+3 V disables auto sweep in delayed timebase; 0 V enables independent timebase function. Grounded in amplifier plugins.
- A/B Sweep − 500 mVp-p, negative-going copy of sweep signal from timebase, not affected by X position control or magnifier; Used for mainframe's Sawtooth Out, additionally fed to V plugins.
- Line Trigger − Approx. 3 VRMS mains-frequency signal from power supply (through transformer).
- Trigger Holdoff − 0/+5 V, generated by time-base, high during holdoff time of time-base, used in mainframe for ALT sequencing.
- Chop Drive − 0/+5 V; switches at one-half the rate of the VERTICAL MODE CHOP signal; high level selects channel 2, low level selects channel 1 of a dual-trace plug-in.
- Aux Sweep Gate − 0/+5 V; pulled high by dual-sweep time-base plug-ins during auxiliary sweep.
- Alt Drive − 0/+5 V; high level will display channel 2 of a dual-trace plug-in, low will display channel 1.
- Intensity Limit − Switched to ground by timebase in slow sweep speeds (≥100 ms/Div), limits beam intensity to protect the CRT phosphor.
- Mainframe Channel Switch − −0.6/+1.1 V logic levels; plug-in output is displayed when MF Channel Switch ≠ MF Mode (XOR).
- Mainframe Mode − 0/+5 V logic levels; plug-in output is displayed when MF Channel Switch ≠ MF Mode (XOR).
- Sweep Inhibit/Sweep Lockout - Mainframe injects current > 1 mA to prevent time base from sweeping. Used for ALT sequencing and delayed sweep of the B time base.
- Delay Gate − negative-going pulse starting at the end of the delay period, and lasting until the end of the sweep from the delaying timebase. Mainframes connect this signal from the A timebase through a 2 k resistor and a diode to B8 Sweep inhibit of the B time base to trigger the delayed sweep. +Gate Output on mainframe uses Delay Gate from H slot B when Delay Gate is selected. Grounded in amplifier plugins.
- Single sweep ready − 0/+5 V, high when single sweep is ready.
- X comp. inhibit − Connected to ground in amplifiers, switched to ground by timebase set to amplifier (X-Y) mode to enable X-Y delay compensation in scopes with that function (7504, 7704, 7904 Opt.2, 7104 Opt.2).
- Signal − Signal output from plugin to mainframe. Differential, 50 Ω per side. 50 mV/Div (differential).
- Trigger − Copy of signal output from V plugin to mainframe. Differential, 50 Ω per side. 50 mV/Div (differential). Terminated on H slots.
- Dual Beam Aux Y-Axis − Used in dual beam mainframes (7844), Current-driven input to mainframe allowing vertical separation of two traces with dual timebase plugins. 1 mA/Div sensitivity.
- Single Sweep Logic − 0/+5 V; high level when time-base is in single sweep mode.
- Single Sweep Reset − Switched to ground to reset single sweep.
- Aux Y Axis − Current-driven input to mainframe allowing vertical separation of two traces with dual timebase plugins. 1 mA/Div sensitivity; driven only when plug-in output is displayed (see MF Ch Switch above).
- Aux Z Axis − Current-driven input to mainframe allowing plugins to modulate beam intensity, e.g. in dual timebase A intensified by B display mode; driven only when plug-in output is displayed (see MF Ch Switch above).
- Trigger In − Trigger signal input on H plugin, routed from V plugin's trigger output. Differential, 50 Ω per side, 50 mV/Div (differential).
- Aux Trigger In − Provided by 1st generation 7000 series mainframes (7704, 7504, 7503, 7403N). Only known use is in the 7B52 timebase as an optional source for the delayed trigger. Four-bay mainframes supply the trigger signal from the left horizontal bay to Aux Trig In on the right horizontal bay and vice versa, via 510 Ω resistors. Three-bay mainframes supply the Left Vert trigger signal via 510 Ω resistors.
- Inter-Plugin Connections − In 1st generation 7000 series mainframes (7704, 7504, 7503, 7403N), pins 26B, 27A/B and 28A/B are inter-plugin connections. In the 3-bay mainframes, right vertical slot pins 27A, 27B, 28A, 28B are connected via 50 Ω striplines to horizontal slot pins 27B, 27A, 28B, 28A respectively, with ground on 26B. Four-slot mainframes additionally make the same connections from the left vertical slot to the right horizontal slot. More information needed - were any plug-ins made that used these?
- GPIB lines − Control signal functions are the same as their IEEE-488 (GPIB) equivalents. Time slot lines 2 to 9 double as IEEE-488 data lines.
- TS1−TS10 − readout system time slot pulses. Idle 0, active −15 V.
- Force Readout − Allows plug-in readout information to be displayed regardless of the mainframe mode switch setting when pulled low (<0.5 V). Used by several 7DXX plug-ins.
- Plugin Mode − 5-level signal providing the mainframe with information about the operating mode of a dual-trace or dual-sweep plugin.
- Ch1/2 Row/Col − Analog current inputs to the readout system. Ch1 refers to the first channel within the plugin slot in question and is associated with the readout field on top of the screen. Ch2 is the 2nd channel displayed at the bottom. Row/Current signals accept negative currents in 100 μA steps; typically, plugins contain resistors from time slot signal lines to row/current lines.
Power Supply Load Limits
According to the 7A17 manual, the total allowed DC power consumption for each plugin is 16.5 W. The individual current limits are shown below.
[note 1] Output from H plugins, input on V plugins
[note 2] Output from V plugins, unused and terminated 50 Ω to ground in mainframe H slots
[note 3] In programmable mainframes, A24 is clamped to not exceed +3 V, indicating to programmable plug-ins to use TS2-TS9 as GPIB lines and a modified readout logic using only TS1 and TS10, with TS1 being active in time slot 1 as in other mainframes, and TS10 being active in each time slot. Programmable plug-ins source at least 100 μA into TS10 (A29) indicating to a programmable mainframe that the alternative time-slot scheme is to be used.
[note 4] Not provided by most mainframes (digitizers only?). 7A16P connects B27 to A9, requires −5.2 V on A27.
[note 5] According to the 11000-series interface manual, many 7k plug-in units ground pin B21 or connect it to pin A21, and The 7D10, 7D11, 7D14, 7S14, and possibly some others have pin A21 grounded.
[note 6] A22 = Busy output from 7D12, 7D15; A22 = Delayed Sweep Gate output for 7B53A with mod. 769G, routed to real panel on 7403 or 7603 scopes with 769H mod.
[note 7] B22 = /Hold input to 7D12, 7D15. Mainframe connection or use unclear.
[note 8] The plug-in mode is supplied to the mainframe either as a resistor connected to ground (with 5% tolerance), or by supplying a DC voltage (with 0.25 V tolerance):
|CH 1, Delaying, Intensified, Normal
|CH 2, Delayed Sweep
|ADD, Mixed Sweep