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7000 Series plug-in interface: Difference between revisions
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* ''Trigger In'' − Trigger signal input on H plugin, routed from V plugin's trigger output. Differential, 50 Ω per side, 50 mV/Div (differential). | * ''Trigger In'' − Trigger signal input on H plugin, routed from V plugin's trigger output. Differential, 50 Ω per side, 50 mV/Div (differential). | ||
* ''Aux Trigger In'' − Provided by 1<sup>st</sup> generation 7000 series mainframes ([[7704]], [[7504]], [[7503]], [[7403N]]). Only known use is in the [[7B52]] timebase as an optional source for the delayed trigger. Four-bay mainframes supply the trigger signal from the left horizontal bay to Aux Trig In on the right horizontal bay and vice versa, via 510 Ω resistors. Three-bay mainframes supply the Left Vert trigger signal via 510 Ω resistors. | * ''Aux Trigger In'' − Provided by 1<sup>st</sup> generation 7000 series mainframes ([[7704]], [[7504]], [[7503]], [[7403N]]). Only known use is in the [[7B52]] timebase as an optional source for the delayed trigger. Four-bay mainframes supply the trigger signal from the left horizontal bay to Aux Trig In on the right horizontal bay and vice versa, via 510 Ω resistors. Three-bay mainframes supply the Left Vert trigger signal via 510 Ω resistors. | ||
* ''Inter-Plugin Connections'' − In 1<sup>st</sup> generation 7000 series mainframes ([[7704]], [[7504]], [[7503]], [[7403N]]), pins 26B, 27A/B and 28A/B are inter-plugin connections. In the 3-bay mainframes, right vertical slot pins 27A, 27B, 28A, 28B are connected via 50 Ω striplines to horizontal slot pins 27B, 27A, 28B, 28A respectively, with ground on 26B. Four-slot mainframes additionally make the same connections from the left vertical slot to the right horizontal slot. | * ''Inter-Plugin Connections'' − In 1<sup>st</sup> generation 7000 series mainframes ([[7704]], [[7504]], [[7503]], [[7403N]]), pins 26B, 27A/B and 28A/B are inter-plugin connections. In the 3-bay mainframes, right vertical slot pins 27A, 27B, 28A, 28B are connected via 50 Ω striplines to horizontal slot pins 27B, 27A, 28B, 28A respectively, with ground on 26B. Four-slot mainframes additionally make the same connections from the left vertical slot to the right horizontal slot. Since no plug-ins were made that used these connections, they were left out from later mainframes. | ||
* ''GPIB lines'' − Control signal functions are the same as their [[GPIB interface|IEEE-488 (GPIB)]] equivalents. Time slot lines 2 to 9 double as IEEE-488 data lines. | * ''GPIB lines'' − Control signal functions are the same as their [[GPIB interface|IEEE-488 (GPIB)]] equivalents. Time slot lines 2 to 9 double as IEEE-488 data lines. | ||
* ''TS1−TS10'' − [[7000 series readout system|readout system]] time slot pulses. Idle 0, active −15 V. | * ''TS1−TS10'' − [[7000 series readout system|readout system]] time slot pulses. Idle 0, active −15 V. | ||