The 7D15 is optimized for timing measurements, having a 100 MHz oscillator and interval measurement averaging capability. It has two inputs and can measure frequency, period or time difference.
The front panel uses SMB connectors for arming, clock in/out and reset signals. The arming input for channel A is active-high whereas that for channel B is active-low. When one or both are connected to the scope's delayed gate output, the delayed timebase can be used to select the part of the signal to be counted, e.g. for burst or A-B interval measurements. With this connection, the arming interval is directly visible as the intensified trace in the "A intensified by B" display mode.
When installed in a horizontal plug-in bay, the 7D15 can use the mainframe's trigger signal as its input. In a vertical bay, it can display the gate signal. In "true gate" mode, this is the actual counter gate, however, this has a low repeat rate due to the counter's dead time. The "pseudo gate" mode improves this by showing the gate whenever the arming and trigger conditions are met, whether the counter is active or not. A third mode shows channel B's gate. The gate display signal is also available on a dedicated BNC output that can be routed to a scope input when the 7D15 is installed in a H slot.
|— Frequency Mode —|
|Input frequency||DC to 225 MHz|
|Resolution||0.1 Hz min.|
|— Period Mode —|
|Range||10 ns to 105 s, Averaging ×1, ×10, ×100 or ×1000|
|Resolution||10 ps max.|
|— Time Interval Mode —|
|Range||6 ns to 105 s, Averaging ×1, ×10, ×100 or ×1000|
|Resolution||0.1 ns usable|
|— Frequency Ratio Mode —|
|Range||10-7 to 104|
|— Totalize Mode —|
|Range||0 to 108 counts|
|— Manual Stopwatch Mode —|
|Range||0 to 105 seconds|
|— Inputs CH A + CH B —|
|Frequency Range||DC (AC coupled: 5 Hz) to 225 MHz|
|Sensitivity||100 mVp-p (from TRIG SOURCE: 0.5 Div)|
|Max. input||200 V DC linearly derated to 20 V at 200 MHz|
|Min. pulse width||5 ns|
|Input impedance||1 MΩ // 22 pF|
The 7D15 uses a number of Tek-made custom chips. The 155-0086-00, 155-0087-00 and 155-0088-00 legend generators are specific to this plug-in. The 155-0090-00 or 155-0171-00 four decade counter/latch/DAC chips implement the lower six counter digits. For the topmost two digits, the 7D15 employs ECL counters. ECL logic requires a −5 V supply, which a switching regulator (board A8) generates from the −15 V rail.
The 5 MHz signal from the (non-ovenized) internal reference crystal oscillator is divided down to a 1 MHz master clock. Optionally, the 1 MHz can be supplied externally as well. An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements.
- Tekscope Vol. 4 No. 5, 1972: The Oscilloscope Controlled Counter
- TekScope Vol. 7 No. 5, 1975 p.15+: Dave McCullough, Delayed gate aids oscilloscope digital measurements
- Tek 7D15 page @ amplifier.cd
- Tek 7D15 page @ barrytech.com
Cam switch with contacts on both sides of the PCB
Custom ICs used in the 7D15
|Page||Class||Manufacturer||Model||Part nos||Description||Designers||Used in|
|155-0086-00||Monolithic integrated circuit||Tektronix||M165||155-0086-00||custom legend generator||Mike Metcalf • Roger McCoy||7D15|
|155-0087-00||Monolithic integrated circuit||Tektronix||M166||155-0087-00||custom legend generator||Mike Metcalf • Roger McCoy||7D15|
|155-0088-00||Monolithic integrated circuit||Tektronix||M167||155-0088-00||custom legend generator||Mike Metcalf • Roger McCoy||7D15 • 7L13 • 7L14|
|155-0090-00||Monolithic integrated circuit||Tektronix||M059||155-0090-00 • 155-0090-01 • 155-0090-02||four-decade counter||Mike Metcalf||7D01 • 7D12 • 7D15 • 7B85 • 7J20|
|155-0171-00||Monolithic integrated circuit||Tektronix||M150A||155-0171-00||4-decade counter, latch and D/A converter||Mike Metcalf||7B85 • 7D01 • 7D12 • 7D15 • 7J20|
|M092||Monolithic integrated circuit||Tektronix||M092||155-0086-00 • 155-0087-00 • 155-0088-00 • 155-0104-00 • 155-0105-00||legend generator||Roger McCoy • Mike Metcalf||7D15 • 7J20|