P7001: Difference between revisions
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{{Spec | Memory | four waveforms, 512 samples each (4K × 10 bit core, or multiple 1k × 10 bit or 2k × 10 bit RAM boards) }} | {{Spec | Memory | four waveforms, 512 samples each (4K × 10 bit core, or multiple 1k × 10 bit or 2k × 10 bit RAM boards) }} | ||
{{Spec | Sampling rate | 150 kHz ±30 kHz }} | {{Spec | Sampling rate | 150 kHz ±30 kHz }} | ||
{{Spec | Single shot performance | 500us/DIV }} | |||
{{Spec | External interface | 16 bit parallel, proprietary "[[CP bus]]" (dual 37-pin [[Sub-D connector]]s) interfacing with Tektronix CP-1100 or CP-4100 series controllers }} | {{Spec | External interface | 16 bit parallel, proprietary "[[CP bus]]" (dual 37-pin [[Sub-D connector]]s) interfacing with Tektronix CP-1100 or CP-4100 series controllers }} | ||
{{EndSpecs}} | {{EndSpecs}} | ||
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The Display Generator card generates the CRT display of either real-time computer output (XY mode) or data stored in the processsors memory (XT mode). Any combination of the stored and acquired waveforms may be displayed simultaneously. Also, since the display generator operates independent of other devices, changing data may be viewed during a store operation. The Display Generator card has a set of jumpers which switch the CRT output between vector and dot display. | The Display Generator card generates the CRT display of either real-time computer output (XY mode) or data stored in the processsors memory (XT mode). Any combination of the stored and acquired waveforms may be displayed simultaneously. Also, since the display generator operates independent of other devices, changing data may be viewed during a store operation. The Display Generator card has a set of jumpers which switch the CRT output between vector and dot display. | ||
===Sample & Hold=== | |||
The functionality of the Sample & Hold card can be divided into 3 areas: Display switching, sampling and multiplexing. The display switching section determines which waveform (real time or stored) is sent to the CRT and is designed around two Tek-made analog multiplexer chips [[155-0022-00]]. A fast [[sampling diodes|four-diode sample and hold circuit]] is the heart of the sampling circuit. Regardless of sweep speed, the sample & Hold card takes a sample every 6.5us. At first the vertical axis is sampled, 95 nanoseconds later the horizontal axis and the blanking. In the last stage the sampled signals are time-multiplexed to provide one output to the A/D converter. The complete timing of the sample & hold circuits is controlled by the A/D Converter card. | |||
===Hardware Signal Averager=== | ===Hardware Signal Averager=== |
Revision as of 09:18, 9 August 2019
The Tektronix P7001 is a digitizer, processor, and memory for the 7704A oscilloscope. The P7001 can also be connected to an external computer which then is able to process the digitized signals. The complete system was called "Digital Processing Oscilloscope" or "DPO" for short and was presented to the public on 26 March 1973 at the IEEE Intercon in New York City.
The design of the P7001 assumes it will be part of a 7704A system, and that the 7704A will be displaying a steady trace. The vertical and horizonal plug-ins control the beam as they would in any 7000-series scope.
The P7001 periodically samples the horizontal and vertical signals simultaneously as they pass from the plug-ins to the vertical and horizontal amplifiers. This allows it to fill its memory with data points represented as coordinate pairs, (x1,y1), (x2,y2), (x3,y3), etc. It is not necessary that x2 be greater than x1, i.e. the samples can be taken out-of-order with respect to their equivalent time in the waveform.
Key Specifications
Bandwith | 175MHz |
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Resolution | 10 bit (V), 9 bit (H) |
Memory | four waveforms, 512 samples each (4K × 10 bit core, or multiple 1k × 10 bit or 2k × 10 bit RAM boards) |
Sampling rate | 150 kHz ±30 kHz |
Single shot performance | 500us/DIV |
External interface | 16 bit parallel, proprietary "CP bus" (dual 37-pin Sub-D connectors) interfacing with Tektronix CP-1100 or CP-4100 series controllers |
Links
Catalog / Specs
- P7001 Spec 1973
- P7001 Spec 1974
- P7001 Spec 1975
- P7001 Spec 1976
- P7001 Spec 1977
- P7001 Spec 1978
- P7001 Spec 1979
- P7001 Spec 1980
- P7001 Spec 1981
Advertising
Internals
The signal coming from the acquisition unit enters a fast four-diode sample and hold circuit where it is sampled at 150 ksamples/sec. Each sample is digitized using a successive-approximation scheme. The analog to digital converter is made of several chips: a digital to analog converter, a comparator, and control logic.
The P7001 has its own power supply built into it, independent of the power supply in the acquisition unit of the 7704A.
The Acquisition Unit of the 7704A, the P7001 Processor, and the Display Unit of the 7704A are connected by the Acquisition-Processor-Display (APD) Interface.
Asynchronus Bus
To provide maximum flexibility all P7001 circuit cards are connected over an 16 bit asynchronous bus with 13 address lines. The bus is mostly implemented as etched lines on the Main Interface Board. Only some High speed signals are sent through coaxial cables that connect to the cards using Peltola connectors. A serially connected line, or daisy chain, in the bus establishes device priority. This signal is called "Data Channel Grant Line". Each card has a specific location in the DPO. The position determines the priority that each card has in the use of the address and data buses. Unused slots must be fitted with a jumper card to close the daisy chain.
Memory
Several types of memory configurations were available: 1k, 2k, 3k or 4k semiconductor memory and also 4k non-volatile core memory. All configurations were available through the whole lifecycle of the P7001. The memory serves to store the acquired waveforms and their associated scale factors. It also stores the computer output for display. Depending on the configuration the following storing capabilites are available:
Configuration | Waveforms | Readout Scale factors |
Messages |
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1k with readout | 1 | 1 | 3 |
1k no readout(*) | 2 | 0 | 0 |
2k with readout | 2 | 2 | 4 |
2k no readout(*) | 4 | 0 | 0 |
3k | 4 | 1 | 4 |
4k | 4 | 4 | 12 |
* Removing the Readout-Interface card doubles the space for storing waveforms but eliminates the capability of displaying text information.
Readout Interface
There are two readout devices in the DPO. One is the readout board in the acquisition unit of the 7704A and the other is the readout interface card in the P7001. In the modes "PLUG-INS" or "STORE" all readout information displayed on the CRT come directly from the plugins. In "STORE" mode the readout interface digitizes these information, converts them to ASCII-data and stores it in memory. In the modes "BOTH" or "MEMORY" the readout interface converts the ASCII data back to readout information and displays them on the CRT.
Display Generator
The Display Generator card generates the CRT display of either real-time computer output (XY mode) or data stored in the processsors memory (XT mode). Any combination of the stored and acquired waveforms may be displayed simultaneously. Also, since the display generator operates independent of other devices, changing data may be viewed during a store operation. The Display Generator card has a set of jumpers which switch the CRT output between vector and dot display.
Sample & Hold
The functionality of the Sample & Hold card can be divided into 3 areas: Display switching, sampling and multiplexing. The display switching section determines which waveform (real time or stored) is sent to the CRT and is designed around two Tek-made analog multiplexer chips 155-0022-00. A fast four-diode sample and hold circuit is the heart of the sampling circuit. Regardless of sweep speed, the sample & Hold card takes a sample every 6.5us. At first the vertical axis is sampled, 95 nanoseconds later the horizontal axis and the blanking. In the last stage the sampled signals are time-multiplexed to provide one output to the A/D converter. The complete timing of the sample & hold circuits is controlled by the A/D Converter card.
Hardware Signal Averager
For DPOs which are connected via the fast CP bus, it is no problem to transfer several data sets over the interface and then have the computer calculate the averaged waveform. But with the relatively slow interfaces like GPIB this procedure is impractical. The optional HSA card solves this problem by locally computing the averaged waveform of up to 4096 single waveforms. The HSA card also has the ability to calculate the histogram of a waveform. The histogram will be displayed horizontally at the lower third of the CRT.
External Interfaces
The external interface card provides a bilateral link between the P7001 and an external controller. The controller has full access to all programmable functions in the Processor, and the P7001, in turn, may interrupt the controller at any time. During the production time of the P7001, the following interfaces were gradually developed:
Description | Part Number | Manual |
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DPO to Data General Nova | 021-0113-00 | 070-1776-00.pdf |
DPO to APD (CP Bus) | 021-0116-00 | 070-1654-00.pdf |
DPO to CP1100 (CP Bus) | 021-0117-00 | 070-1654-01.pdf |
DPO to TEK31 calculator | 021-0127-00 | 070-1777-00.pdf |
DPO to CAMAC | 021-0146-00 | |
DPO to 4010 Family | 021-0175-00 | 070-1936-00.pdf |
DPO to GPIB | 021-0206-00 | 070-2623-00.pdf |
Pictures
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Front panel
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P7001 in 7704A
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P7001 in 7704A
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Internal
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Top view
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Front of backplane
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main interface board (backplane)
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Rear of backplane
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Interunit connector
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Interunit connector
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Interunit connector
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Switching power supply
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front panel rear
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extender boards
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"Dummy-card" or official called "Data Channel Grant jumper card". Needs to be installed in empty slots of Backplane.
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Data Channel Grant Card
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Bus Priority of a fully equipped P7001
Keyboard overlay cards
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blank card for user definable programs
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Two examples of original overlay cards
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Example of aftermarket overlay cards
External Interfaces (optional)
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CPBus interface mounted
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CP Bus Interface front
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CP Bus Interface rear
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GPIB Interface IO board
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GPIB Interface IO board with shielding
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GPIB Interface CPU board
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Modern clone of the P7001 GPIB interface
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Modern clone of the P7001 GPIB interface
Sample and Hold Card
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Vertical sampling bridge
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Horizontal sampling bridge
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Sampling strobe generator
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Sample and hold edge connector
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Sample and hold transformers
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Sample and hold transformer
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Sample and hold rear
Core Memory (optional)
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Address decoder
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Core boards
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Core memory
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Core closeup
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Core closeup
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High Resolution view of partial core module
Semiconductor memory (optional)
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2K semiconductor memory (aka "MOS")
ADC and Display
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Front panel connections
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ADC
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ADC rear
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Probe points on ADC
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Display generator
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Display generator rear
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Z-axis and panel controller
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Z-axis and panel controller rear
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Readout interface
Hardware signal Averager (HSA)
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HSA timing board. The HSA module (optional) performs signal averaging and can calculate a histogram.
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HSA memory board.
Schematics
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Block Diagram
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Address map of a fully equipped P7001
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Power supply schematic 1
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Power supply schematic 2
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APD Interconnect
Cofigurations
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Example of Calculator based system (WP1100) in 1974
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Example of Calculator based system (WP1100) in 1978
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Example of Controller based system (WP1200) in 1973
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Example of Controller based system (WP1200) in 1975
Workflow with connected Controller
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With pressing a program-call button on the P7001...
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.. the displayed signal is digitized...
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...and transferred to the Controller...
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...the Controller does some calculations...
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...and transfers the result back to the P7001
X/Y Mode for external Controller
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A connected computer has direct access to the Display Generator. This allows software-controlled live movements of the Beam.
Design Team
Notable Members of the Design Team were: Hiro Moriyasu, Bruce Hamilton, Luis Navarro, Bob Shand and Jack Gilmore.
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Key design Team of the P7001.