7D01: Difference between revisions
(7D01 pic without DF for template) |
No edit summary |
||
(52 intermediate revisions by 6 users not shown) | |||
Line 1: | Line 1: | ||
{{Plugin Sidebar | {{Plugin Sidebar | ||
|manufacturer=Tektronix | |||
summary=Logic Analyzer | | |series=7000-series scopes | ||
image=Tek 7D01 Front 2.jpg | | |type=7D01 | ||
caption=Tektronix 7D01 without display formatter | | |summary=16-ch Logic Analyzer | ||
introduced= | |image=Tek 7D01 Front 2.jpg | ||
discontinued=1985 | | |caption=Tektronix 7D01 without display formatter | ||
|introduced=1976 | |||
|discontinued=1985 | |||
* [ | |designers=Murlan Kaufman;Keith Taylor;Morris Green;Jeff Bradford;Ed Wolf;Vendell Damm | ||
* [ | |manuals= | ||
* [[Media:070-2205-02.pdf|7D01 Operators Manual]] (OCR) | |||
* [[Media:070-2206-00.pdf|7D01 Instruction Manual 070-2206-00]] (OCR) | |||
* [[Media:070-2206-02.pdf|7D01 Instruction Manual 070-2206-02 Rev. Oct 1982]] (OCR) | |||
* [[Media:Tek_7D01_Anleitung_Deutsch.pdf|Tektronix 7D01 Anleitung]] (Operators Manual, German, OCR) | |||
<small> | |||
'''Alternate copies''' | |||
* [[Media:070-2206-02_2.pdf|7D01 Instruction Manual 070-2206-02 rev. Oct 1982]] (OCR) | |||
'''Brochures''' | |||
* [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976]] | |||
</small> | |||
}} | }} | ||
The '''Tektronix 7D01''' is a logic analyzer plug-in for the [[7000-series scopes]]. | The '''Tektronix 7D01''' is a 16-channel logic analyzer plug-in for the [[7000-series scopes]] that takes two [[P6451]] 8+1 channel probes. | ||
When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields). | |||
When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen [[7603N]]. | |||
Project manager for the 7D01 was [[Murlan Kaufman]]. Project leader was [[Keith Taylor]], with [[Morris Green]] and [[Jeff Bradford]] doing electrical design, and [[Ed Wolf]] mechanical design. [[Wendell Damm]] worked on the active probe. | |||
{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Channels | | {{Spec | Channels | | ||
* 4 channels at 1016 bits/channel | * 4 channels at 1016 bits/channel, maximum external clock period 10 ns (100 MHz) | ||
* 8 channels at 508 bits/channel | * 8 channels at 508 bits/channel, maximum external clock period 20 ns (50 MHz) | ||
* 16 channels at 254 bits/channel | * 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz) | ||
}} | }} | ||
{{Spec | Sampling Rate | 10 ns to 5 ms per sample ( | {{Spec | Sampling Rate | 10 ns to 5 ms per sample (1–2–5) or external clock up to 50 MHz}} | ||
{{Spec | | {{Spec | Trigger Sources | | ||
* external | * external | ||
* channel 0 data | * channel 0 data | ||
Line 27: | Line 44: | ||
}} | }} | ||
{{EndSpecs}} | {{EndSpecs}} | ||
==Links== | ==Links== | ||
* [ | * [https://paulcarbone.com/blog/tekronix-7d01-logic-analyzer/ 7D01 @ paulcarbone.com] (with detailed photos) | ||
* [https://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/logicanalyzer_7D01.htm 7D01 @ amplifier.cd] | |||
* [http://www.barrytech.com/tektronix/tek7000/tek7d01-df1.html 7D01 @ barrytech.com] | * [http://www.barrytech.com/tektronix/tek7000/tek7d01-df1.html 7D01 @ barrytech.com] | ||
{{Documents|Link=7D01}} | |||
{{PatentLinks|7D01}} | |||
==Acquisition== | |||
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock. | |||
The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier. | |||
A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. | |||
The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe. | |||
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V. | |||
There is no internal glitch detector, but a separate [[DL2]] or [[DL502]] latch plug-in can be used to stretch short pulses ≥5 ns to the clock period. | |||
The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output. | |||
==Internals== | |||
The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs. | |||
The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits. | |||
The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails. | |||
There is an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable. ''(Any known uses?)'' | |||
==Notes== | |||
'''Note about external clock rates''' (from Jim Mauck): | |||
''When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.'' | |||
The 7D01 is often affected by [[bad TI IC sockets]], see [[7D01/Repairs|the Repairs tab]]. | |||
==Pictures== | ==Pictures== | ||
<gallery> | <gallery> | ||
Tek-7704a-7D01.jpg | 7D01 in [[7704A]] mainframe | |||
Tek 7d01 and df1 in 7313.jpg|7D01 and [[DF1]] in [[7313]] | |||
Tek df2 7d01 lit.jpg | |||
Tek 7D01 DF1.jpg | 7D01+[[DF1]] Front | |||
Tek_7D01_Front.jpg | 7D01+[[DF1]] Front | |||
Tek_7D01_Left.jpg | 7D01 Left | |||
Tek_7D01_Right.jpg | 7D01 Right | |||
Tek_7D01_Bottom.jpg | 7D01 Bottom | |||
Tek_7D01_rear.jpg | 7D01 Rear (back plate removed) | |||
7d01-df1-front.jpg | |||
7d01-df1-top.jpg | |||
7d01-df1-bottom.jpg | |||
Tek_7D01_Cursor.jpg | 7D01 Cursor Board | |||
Tek_7D01_Memory.jpg | 7D01 Memory Board | |||
Tek_7D01_timing.jpg | Standalone 7D01 Timing Diagram (using mainframe readout) | |||
Tek_7D01-DF01_timing.jpg | 7D01 + [[DF1]]/DF2 Timing Diagram (readout from DF) | |||
Tek_7D01-DF01_table.jpg | 7D01 + [[DF1]]/DF2 State Table | |||
</gallery> | </gallery> | ||
==Components== | |||
{{Parts|7D01}} | |||
[[Category:7000 series special-function plugins]] | [[Category:7000 series special-function plugins]] | ||
[[Category: | [[Category:7000 series logic analyzer plugins]] |
Latest revision as of 11:43, 19 June 2024
The Tektronix 7D01 is a 16-channel logic analyzer plug-in for the 7000-series scopes that takes two P6451 8+1 channel probes.
When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's readout system to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).
When combined with an optional DF1 or DF2 display formatter (attached to the left of the 7D01 through a DD-50 connector), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen 7603N.
Project manager for the 7D01 was Murlan Kaufman. Project leader was Keith Taylor, with Morris Green and Jeff Bradford doing electrical design, and Ed Wolf mechanical design. Wendell Damm worked on the active probe.
Key Specifications
Channels |
|
---|---|
Sampling Rate | 10 ns to 5 ms per sample (1–2–5) or external clock up to 50 MHz |
Trigger Sources |
|
Links
- 7D01 @ paulcarbone.com (with detailed photos)
- 7D01 @ amplifier.cd
- 7D01 @ barrytech.com
Documents Referencing 7D01
Document | Class | Title | Authors | Year | Links |
---|---|---|---|---|---|
Tekscope 1976 V8 N2.pdf | Article | A 16-channel Logic Analyzer for the 7000 Series | Keith Taylor | 1976 | 7D01 • 7D10 |
Tekscope 1976 V8 N4 with Supplement.pdf | Article | A Display Formatter – The Indispensable Tool for the Data Domain | Dave Lowry • Jeff Bradford | 1976 | DF1 • 7D01 |
AX-3524.pdf | Application Note | Troubleshooting a Microprocessor (Logic Analyzer App Note #57K1.0) | 1977 | 7D01 • DF1 | |
Tekscope 1978 V10 N2.pdf | Article | Unraveling the Mystery on the GPIB | Bruce Ableidinger | 1978 | DF2 • 7D01 • P6451 • GPIB |
Patents that may apply to 7D01
Page | Title | Inventors | Filing date | Grant date | Links |
---|---|---|---|---|---|
Patent US 3562464A | Cam actuated switch having movable and fixed contacts on circuit board | Howard Vollum • Willem H Verhoef • Tony Sprando | 1968-10-07 | 1971-02-09 | Cam switches • 2701 • 2703 • 432 • 434 • 465 • 475 • 5A38 • 5A45 • 7A15 • 7A16A • 7A18 • 7A19 • 7A24 • 7A26 • 7B10 • 7B15 • 7B50 • 7B51 • 7B52 • 7B53A • 7B50A • 7B70 • 7B71 • 7B80 • 7B85 • 7B87 • 7B92 • 7B92A • 7D01 • 7D12 • 7D15 • 7J20 • 7S12 • 7T11 • 7T11A |
Acquisition
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock. The 9th channel on the first probe serves as an external clock input, that on the second probe as an external qualifier.
A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.
There is no internal glitch detector, but a separate DL2 or DL502 latch plug-in can be used to stretch short pulses ≥5 ns to the clock period. The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.
Internals
The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs. The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits.
The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails.
There is an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable. (Any known uses?)
Notes
Note about external clock rates (from Jim Mauck):
When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.
The 7D01 is often affected by bad TI IC sockets, see the Repairs tab.
Pictures
-
7D01 in 7704A mainframe
-
-
7D01+DF1 Front
-
7D01+DF1 Front
-
7D01 Left
-
7D01 Right
-
7D01 Bottom
-
7D01 Rear (back plate removed)
-
-
-
-
7D01 Cursor Board
-
7D01 Memory Board
-
Standalone 7D01 Timing Diagram (using mainframe readout)
-
7D01 + DF1/DF2 Timing Diagram (readout from DF)
-
7D01 + DF1/DF2 State Table
Components
Some Parts Used in the 7D01
Part | Part Number(s) | Class | Description | Used in |
---|---|---|---|---|
155-0090-00 | 155-0090-00 • 155-0090-01 • 155-0090-02 | Monolithic integrated circuit | four-decade counter, latch and D/A converter | 7B85 • 7D01 • 7D12 • 7D15 • 7J20 |
155-0171-00 | 155-0171-00 | Monolithic integrated circuit | four-decade counter, latch and D/A converter | 7B85 • 7D01 • 7D12 • 7D15 • 7J20 |