WR501: Difference between revisions
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==Links== | ==Links== | ||
{{Documents|Link=WR501}} | {{Documents|Link=WR501}} | ||
{{PatentLinks|WR501}} | |||
==Internals== | ==Internals== | ||
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Wr501_left.jpg|Left internal | Wr501_left.jpg|Left internal | ||
Wr501_left2.jpg|Left internal | Wr501_left2.jpg|Left internal | ||
WR501 with DL.jpg | Left internal (unit with delay line fitted) | |||
Wr501_right.jpg|Right internal | Wr501_right.jpg|Right internal | ||
Wr501_connector.jpg|Logic pod connector | Wr501_connector.jpg|Logic pod connector | ||
Tek wr501 block.png|Block diagram | Tek wr501 block.png|Block diagram | ||
</gallery> | </gallery> | ||
Latest revision as of 05:23, 6 October 2024
The Tektronix WR501 is a 16-channel word recognizer plug-in for the TM500 system.
Key Specifications
- please add
The WR 501 word recognizer takes, as its inputs:
- 16 digital input signals (through two P6451 probes)
- specification of the 16-bit trigger word, including any don't-care bits
It produces a pulse at its output when the trigger word is recognized.
Links
Documents Referencing WR501
| Document | Class | Title | Authors | Year | Links |
|---|---|---|---|---|---|
| Tekscope 1976 V8 N2.pdf | Article | A Plug-in Word Recognizer with Digital Delay | Pete Janowitz | 1976 | WR501 • LA501 • LA501W |
| 070-2088-04.pdf | Book | TM500 Series Rear Interface Data Book | 1985 | AA501 • AF501 • AM501 • AM502 • AM503 • AM511 • DC501 • DC502 • DC503 • DC503A • DC504 • DC505 • DC505A • DC508 • DC508A • DC509 • DC510 • DC5009 • DC5010 • DD501 • DL502 • DM501 • DM501A • DM502 • DM502A • DM505 • DM5010 • FG501 • FG501A • FG502 • FG503 • FG504 • FG507 • FG5010 • LA501 • LA501W • WR501 • MR501 • PG501 • PG502 • PG505 • PG506 • PG507 • PG508 • PS501 • PS502 • PS503 • PS503A • PS505 • PS5010 • RG501 • SC501 • SC502 • SC503 • SC504 • SG502 • SG503 • SG504 • SG505 • SW503 • TG501 • TR501 • TR502 • MI5010 • MX5010 • SI5010 |
Internals
Most of the logic in the WR 501 is ECL, and is rated to operate up to about 50 MHz. It has synchronous (clocked) and asynchronous (unclocked) modes.
The WR 501 includes a delay function and can provide a trigger signal for an oscilloscope or provide a trigger signal and data acquisition for the LA501 Logic Analyzer.
Note that DL15 and DL115, the 24-pin delay lines that fit in the sockets on each board are only found on units that were interconnected to an LA 501. The empty socket for DL15 is visible in the pictures below, on the A1 daughter board. The socket for DL115 is on the board underneath A1, on the A2 main board. They are unnecessary if you are using the WR501 to trigger a scope.
These ECL delay lines, P/N 119-0775-00, 10 ns, 100 Ω, can be found in the 7D01 logic analyzer plugin for the 7000-series scopes.
Pictures
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Front
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Left internal
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Left internal
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Left internal (unit with delay line fitted)
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Right internal
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Logic pod connector
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Block diagram
