DC505: Difference between revisions
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* [ | {{TM500 | mfg=Tektronix | type=DC505 | function=225 MHz counter/timer | class=counter | image=Tek dc505.jpg | introduced=1974 | discontinued=1976 | | ||
|manuals= | |||
* [[Media:070-1665-00.pdf|Tektronix DC505 Manual]] (OCR) | |||
}} | |||
It was superseded by the [[DC505A]] in 1976. | |||
{{BeginSpecs}} | |||
{{Spec | Frequency range | 0 Hz (DC coupled) / 10 Hz (AC coupled) to 225 MHz }} | |||
{{Spec | Sensitivity | 50 mV<sub>RMS</sub> to 150 MHz, 100 mV<sub>RMS</sub> to 225 MHz (sine) }} | |||
{{Spec | Resolution | 7 digits }} | |||
{{Spec | Gate time | 0.01 s to 10 s in decade steps }} | |||
{{Spec | Stability | Standard: 1×10<sup>−5</sup>; Opt.1: 5×10<sup>−7</sup> (0°C to +50°C, after 30 min warm-up) }} | |||
{{Spec | Long-term drift | Standard: 1×10<sup>−5</sup> per month; Opt.1: 5×10<sup>−7</sup> per month }} | |||
{{Spec | Features | | |||
* Two input channels (BNC connectors) | |||
* Functions: Frequency, frequency ratio, period, interval, pulse width, events | |||
}} | |||
{{Spec | Options | | |||
* Opt.1: 5 MHz TCXO (with ÷5 divider) | |||
}} | |||
{{EndSpecs}} | |||
==Links== | |||
* [http://www.barrytech.com/tektronix/tektm500/tekdc505.html DC505 @ barrytech.com] | |||
{{Documents|Link=DC505}} | |||
==Rear Interface== | |||
<small> | |||
{| class="wikitable" | |||
|- | |||
! Connector Pin | |||
! Signal | |||
! Connector Pin | |||
! Signal | |||
|- | |||
| || || 27A || Internal Scan Clock Disable | |||
|- | |||
| 26B || Manual Start-Stop || 26A || /RESET | |||
|- | |||
| 25B || Internal Scan Clock Out || 25A || Time Slot Zero | |||
|- | |||
| 24B || Internal Scan Clock Out || || | |||
|- | |||
| 23B || Overflow || || | |||
|- | |||
| 21B || BCD output 2 || || | |||
|- | |||
| 20B || BCD output 8 || 20A || BCD output 4 | |||
|- | |||
| 19B || Data Good || 19A || BCD output 1 | |||
|- | |||
| || || 14A || Ext Clock Input<br />Int 1 MHz out via 200 Ω | |||
|} | |||
</small> | |||
Data is output serially by digit. | |||
[[ | ==Internals== | ||
[[ | An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements. | ||
The DC505 uses a mix of ECL and TTL dividers and logic, and a [[Mostek MK5007]] four-decade counter/latch/multiplexer (U700). Unlike the similarly-specified [[7D15]], it employs no Tek made custom ICs. | |||
The first counter decade is implemented as a divide-by-2 ECL flip-flop (U342, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain. | |||
In the power supply, a 723 regulator provides +5 V from the 17.5 V<sub>AC</sub> mainframe rails using the mainframe's NPN pass transistor. Its output includes a zener/SCR crowbar circuit. Another 723 provides +15 V from the +33 V rail. A discrete regulator using the PNP pass transistor produces –10 V from the –33 V rail. | |||
==Pictures== | |||
<gallery> | |||
Tek dc505.jpg | |||
DC505 left.jpg | |||
DC505 right.jpg | |||
DC505 front 2.jpg | |||
</gallery> | |||
{{BetterPics}} | |||
==Components== | |||
{{Parts|DC505}} |
Revision as of 06:21, 4 March 2024
The Tektronix DC505 is a 225 MHz counter/timer plug-in for the TM500 system.
It was superseded by the DC505A in 1976.
Key Specifications
Frequency range | 0 Hz (DC coupled) / 10 Hz (AC coupled) to 225 MHz |
---|---|
Sensitivity | 50 mVRMS to 150 MHz, 100 mVRMS to 225 MHz (sine) |
Resolution | 7 digits |
Gate time | 0.01 s to 10 s in decade steps |
Stability | Standard: 1×10−5; Opt.1: 5×10−7 (0°C to +50°C, after 30 min warm-up) |
Long-term drift | Standard: 1×10−5 per month; Opt.1: 5×10−7 per month |
Features |
|
Options |
|
Links
Documents Referencing DC505
Rear Interface
Connector Pin | Signal | Connector Pin | Signal |
---|---|---|---|
27A | Internal Scan Clock Disable | ||
26B | Manual Start-Stop | 26A | /RESET |
25B | Internal Scan Clock Out | 25A | Time Slot Zero |
24B | Internal Scan Clock Out | ||
23B | Overflow | ||
21B | BCD output 2 | ||
20B | BCD output 8 | 20A | BCD output 4 |
19B | Data Good | 19A | BCD output 1 |
14A | Ext Clock Input Int 1 MHz out via 200 Ω |
Data is output serially by digit.
Internals
An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements.
The DC505 uses a mix of ECL and TTL dividers and logic, and a Mostek MK5007 four-decade counter/latch/multiplexer (U700). Unlike the similarly-specified 7D15, it employs no Tek made custom ICs. The first counter decade is implemented as a divide-by-2 ECL flip-flop (U342, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain.
In the power supply, a 723 regulator provides +5 V from the 17.5 VAC mainframe rails using the mainframe's NPN pass transistor. Its output includes a zener/SCR crowbar circuit. Another 723 provides +15 V from the +33 V rail. A discrete regulator using the PNP pass transistor produces –10 V from the –33 V rail.
Pictures
Better pictures needed - please contribute
Components
Some Parts Used in the DC505
Part | Part Number(s) | Class | Description | Used in |
---|---|---|---|---|
2N4249 | 151-0342-00 | Discrete component | PNP Si low noise amp. | DC501 • DC502 • DC503 • DC503A • DC504 • DC504A • DC505 • DC505A • DC508 • DC508A • DC509 • DC510 |
Mostek MK5007 | 156-0409-00 | Monolithic integrated circuit | four-decade BCD counter with latches and output multiplexer | 213 • DC505 • DC505A |