DC505: Difference between revisions
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Data is output serially by digit. | Data is output serially by digit. | ||
==Internals== | |||
An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements. | |||
The DC505A uses a mix of ECL and TTL dividers and logic, and a [[Mostek MK5007]] four-decade counter/latch/multiplexer (U700). Unlike the similarly-specified [[7D15]], it employs no Tek made custom ICs. | |||
The first counter decade is implemented as a divide-by-2 ECL flip-flop (U342, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain. | |||
In the power supply, the +5 V section, controlled by a 723, uses the mainframe's NPN pass transistor and includes a zener/SCR crowbar circuit. A discrete regulator using the PNP pass transistor produces - V from the -33 V rail. | |||
==Pictures== | ==Pictures== |
Revision as of 06:49, 21 November 2023
The Tektronix DC505 is a 225 MHz counter/timer plug-in for the TM500 system.
It was superseded by the DC505A in 1976.
Key Specifications
Frequency range | 0 Hz (DC coupled) / 10 Hz (AC coupled) to 225 MHz |
---|---|
Sensitivity | 50 mVRMS to 150 MHz, 100 mVRMS to 225 MHz (sine) |
Resolution | 7 digits |
Gate time | 0.01 s to 10 s in decade steps |
Stability | Standard: 1×10−5; Opt.1: 5×10−7 (0°C to +50°C, after 30 min warm-up) |
Long-term drift | Standard: 1×10−5 per month; Opt.1: 5×10−7 per month |
Features |
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Links
Documents Referencing DC505
Rear Interface
Connector Pin | Signal | Connector Pin | Signal |
---|---|---|---|
27A | Internal Scan Clock Disable | ||
26B | Manual Start-Stop | 26A | /RESET |
25B | Internal Scan Clock Out | 25A | Time Slot Zero |
24B | Internal Scan Clock Out | ||
23B | Overflow | ||
21B | BCD output 2 | ||
20B | BCD output 8 | 20A | BCD output 4 |
19B | Data Good | 19A | BCD output 1 |
14A | Ext Clock Input |
Data is output serially by digit.
Internals
An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements.
The DC505A uses a mix of ECL and TTL dividers and logic, and a Mostek MK5007 four-decade counter/latch/multiplexer (U700). Unlike the similarly-specified 7D15, it employs no Tek made custom ICs. The first counter decade is implemented as a divide-by-2 ECL flip-flop (U342, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain.
In the power supply, the +5 V section, controlled by a 723, uses the mainframe's NPN pass transistor and includes a zener/SCR crowbar circuit. A discrete regulator using the PNP pass transistor produces - V from the -33 V rail.
Pictures
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DC505
Components
Some Parts Used in the DC505
Part | Part Number(s) | Class | Description | Used in |
---|---|---|---|---|
2N4249 | 151-0342-00 | Discrete component | PNP Si low noise amp. | DC501 • DC502 • DC503 • DC503A • DC504 • DC504A • DC505 • DC505A • DC508 • DC508A • DC509 • DC510 |
Mostek MK5007 | 156-0409-00 | Monolithic integrated circuit | four-decade BCD counter with latches and output multiplexer | 213 • DC505 • DC505A |