DC505A

The Tektronix DC505A is a 225 MHz counter/timer plug-in for the TM500 system.

Manuals – Specifications – Links – Pictures

The predecessor of the DC505A was the DC505.

Key Specifications

Frequency range	0 Hz (DC coupled) / 10 Hz (AC coupled) to 225 MHz
Sensitivity	50 mVRMS to 150 MHz, 100 mVRMS to 225 MHz (sine)
Resolution	7 digits max.
Gate time	0.01 s to 10 s in decade steps
Stability	Standard: 1×10−5; Opt.1: 5×10−7 (0°C to +50°C, after 30 min warm-up)
Long-term drift	Standard: 1×10−5 per month; Opt.1: 5×10−7 per month
Features	Two input channels (BNC connectors) Functions: Frequency, frequency ratio, period, interval, pulse width, events Trigger level monitor output
Options	Opt.1: 5 MHz TCXO (with ÷5 divider) Opt.4: Decimal point output on rear interface (for use with 153 interface)

Links

Rear Interface

Connector Pin	Signal	Connector Pin	Signal
27B	DP5 (Opt.4 only)	27A	Internal Scan Clock Disable
26B	Manual Start-Stop	26A	/RESET
25B	Internal Scan Clock Out	25A	Time Slot Zero
24B	Internal Scan Clock Out
23B	Overflow
		22A	Trig Level Out
21B	BCD output 2
20B	BCD output 8	20A	BCD output 4
19B	Data Good	19A	BCD output 1
18B	DP4 (Opt.4 only)
17B	Ch B Input	17A	Ch A GND
16B	Ch B GND	16A	Ch A Input
15B	DP3 (Opt.4 only)	15A	DP1 (Opt.4 only)
14B	DP2 (Opt.4 only)	14A	Ext Clock Input / 1 MHz Out

Data is output serially by digit.

The rear interface inputs are selected by pulling out the LEVEL knob.

Internals

The manual warns that if multiple 505As with serial numbers B010630 and above are installed in low-power compartments of a TM500 mainframe, the mainframe needs to be modified to allow for the extra current draw. The required modifications are described in the DC505A manual.

An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements.

The DC505A uses a mix of ECL and TTL dividers and logic, and a Mostek MK5007 four-decade counter/latch/multiplexer (U700). Unlike the similarly-specified 7D15, it employs no Tek made custom ICs. The first counter decade is implemented as a divide-by-2 ECL flip-flop (U350, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain.

In the power supply, the +5 V section, controlled by a 723, uses the mainframe's NPN pass transistor and includes a zener/SCR crowbar circuit. A discrete regulator using the PNP pass transistor produces - V from the -33 V rail.

Pictures

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  DC505A

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  DC505A

Components