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The Tektronix P7001 is a digitizer, processor, and memory for the 7704A oscilloscope. The P7001 can also be connected to an external computer which then is able to process the digitized signals. The complete system was called "Digital Processing Oscilloscope" or "DPO" for short and was presented to the public on 26 March 1973 at the IEEE Intercon in New York City.

The design of the P7001 assumes it will be part of a 7704A system, and that the 7704A will be displaying a steady trace. The vertical and horizontal plug-ins control the beam as they would in any 7000-series scope.

The P7001 periodically samples the horizontal and vertical signals simultaneously as they pass from the plug-ins to the vertical and horizontal amplifiers. This allows it to fill its memory with data points represented as coordinate pairs, (x1,y1), (x2,y2), (x3,y3), etc. It is not necessary that x2 be greater than x1, i.e. the samples can be taken out-of-order with respect to their equivalent time in the waveform.

Key Specifications

Bandwidth 175 MHz
Resolution 10 bit (V), 9 bit (H)
Memory four waveforms, 512 samples each (4K × 10 bit core, or multiple 1k × 10 bit or 2k × 10 bit RAM boards)
plus 12 messages with 80 characters
Sampling rate 150 kHz ±30 kHz
Single-shot performance 500 μs/Div
External interface 16 bit parallel, proprietary "CP bus" (dual 37-pin Sub-D connectors) interfacing with Tektronix CP-1100 or CP-4100 series controllers; other interfaces available
Power 115 V, 60 Hz; 7704A: 180 W, P7001: 120 W
Dimensions 12" (30.6 cm) W × 18.9" (47.5 cm) H × 22.7" (57.7 cm) D
Weight 48 lbs (21.8 kg) without plugins
Temperature Range 0°C to +50°C operating


Documents Referencing P7001

Document Class Title Authors Year Links
Tekscope 1973 V5 N2 Mar 1973.pdf Article The Oscilloscope with Computing Power Hiro Moriyasu Luis Navarro Jack Gilmore Bruce Hamilton 1973


The signal coming from the acquisition unit enters a fast four-diode sample and hold circuit where it is sampled at 150 ksamples/sec. Each sample is digitized using a successive-approximation scheme. The analog to digital converter is made of several chips: a digital to analog converter, a comparator, and control logic.

The P7001 has its own power supply built into it, independent of the power supply in the acquisition unit of the 7704A.

The Acquisition Unit of the 7704A, the P7001 Processor, and the Display Unit of the 7704A are connected by the Acquisition-Processor-Display (APD) Interface.

Asynchronus Bus

To provide maximum flexibility all P7001 circuit cards are connected over an 16 bit asynchronous bus with 13 address lines. The bus is mostly implemented as etched lines on the Main Interface Board. Only some High speed signals are sent through coaxial cables that connect to the cards using Peltola connectors. A serially connected line, or daisy chain, in the bus establishes device priority. This signal is called "Data Channel Grant Line". Each card has a specific location in the DPO. The position determines the priority that each card has in the use of the address and data buses. Unused slots must be fitted with a jumper card to close the daisy chain.

Front Panel & Z-Axis boards

The Front Panel board contains coding and debouncing logic for the 28 pushbuttons and driver logic for the 15 status indicators. The Z-Axis/Front panel card contains circuits for system control and the P7001 status latches. Bus termination, Z-Axis switching circuits and Z Axis Valid sensing are also located on this card. Eighteen of the front-panel buttons are used to communicate with the computer. The SEND and RECEIVE buttons direct the computer to transfer waveforms. The 16 Program call buttons on the right side of the front panel are used to execute user-definable programs on the computer.


Several types of memory configurations were available: 1k, 2k, 3k or 4k semiconductor memory and also 4k non-volatile core memory. All configurations were available through the whole lifecycle of the P7001. The memory serves to store the acquired waveforms and their associated scale factors. It also stores the computer output for display. Depending on the configuration the following storing capabilities are available:

Configuration Waveforms Readout
Scale factors
1k with readout 1 1 3
1k no readout(*) 2 0 0
2k with readout 2 2 4
2k no readout(*) 4 0 0
3k 4 1 4
4k 4 4 12

* Removing the Readout-Interface card doubles the space for storing waveforms but eliminates the capability of displaying text information.

Readout Interface

There are two readout devices in the DPO. One is the readout board in the acquisition unit of the 7704A and the other is the readout interface card in the P7001. In the modes "PLUG-INS" or "STORE" all readout information displayed on the CRT come directly from the plugins. In "STORE" mode the readout interface digitizes these informations, converts them to ASCII-data and stores it in memory. In the modes "BOTH" or "MEMORY" the readout interface converts the ASCII data back to readout information and displays them on the CRT.

Display Generator

The Display Generator card generates the CRT display of either real-time computer output (XY mode) or data stored in the processors memory (XT mode). Any combination of the stored and acquired waveforms may be displayed simultaneously. Also, since the display generator operates independent of other devices, changing data may be viewed during a store operation. The Display Generator card has a set of jumpers which switch the CRT output between vector and dot display.

Sample & Hold

The functionality of the Sample & Hold card can be divided into 3 areas: Display switching, sampling and multiplexing. The display switching section determines which waveform (real time or stored) is sent to the CRT and is designed around two Tek-made analog multiplexer chips 155-0022-00. A fast four-diode sample and hold circuit is the heart of the sampling circuit. Regardless of sweep speed, the sample & Hold card takes a sample every 6.5us. At first the vertical axis is sampled, 95 nanoseconds later the horizontal axis and the blanking. In the last stage the sampled signals are time-multiplexed to provide one output to the A/D converter. The complete timing of the sample & hold circuits is controlled by the A/D Converter card.

A/D Converter

The A/D Converter uses a successive approximation technique to digitize the vertical and horizontal samples. The vertical resolution is 10 bits, the horizontal resolution 9 bits. It is worth mentioning that the vertical part of the signal is digitized in a range of 10 divisions. As a result, even signal components that are slightly above or below the screen edge are captured. A two bit memory location code (A, B, C or D) is added to the converted horizontal data. The result is the direct memory address at which the vertical data is stored to. For sweeps slower or equal to 500 μs/Div all 512 waveform points are digitized in one sweep. For faster sweep speeds the samples will be taken out-of-order with respect to their equivalent time in the waveform. In this case subsequent sweeps are needed complete the digitized data. The computer has direct access to the register of the A/D converter and may at any time read the last vertical sample. This makes it possible to create arrays with more than 512 elements.

Hardware Signal Averager

For DPOs which are connected via the fast CP bus, it is no problem to transfer several data sets over the interface and then have the computer calculate the averaged waveform. But with the relatively slow interfaces like GPIB this procedure is impractical. The optional HSA card solves this problem by locally computing the averaged waveform of up to 4096 single waveforms. The HSA card also has the ability to calculate the histogram of a waveform. The histogram will be displayed horizontally at the lower third of the CRT.

External Interfaces

The external interface card provides a bilateral link between the P7001 and an external controller. The controller has full access to all programmable functions in the Processor, and the P7001, in turn, may interrupt the controller at any time. During the production time of the P7001, the following interfaces were gradually developed:

Description Part Number Manual
DPO to Data General Nova 021-0113-00 070-1776-00
DPO to APD (CP Bus) 021-0116-00 070-1654-00
DPO to CP1100 (CP Bus) 021-0117-00 070-1654-01
DPO to TEK31 calculator 021-0127-00 070-1777-00
DPO to CAMAC 021-0146-00 ?
DPO to 4010 Family 021-0175-00 070-1936-00
DPO to GPIB 021-0206-00 070-2623-00

Power Supply

The power supply in the P7001 is a reduced version of the power supply in the 7704A. Both power supplies are connected together using a relay in a master-slave configuration.



Keyboard overlay cards

External Interfaces (optional)

Sample and Hold Card

Core Memory (optional)

Semiconductor memory (optional)

ADC and Display

Hardware signal Averager (HSA)



Workflow with connected Controller

X/Y Mode for external Controller

Design Team

Key design Team of the P7001 (click to enlarge)


Scope-Mobile Carts

At least 3 different Scope-Mobile Carts were designed in order to be able to move the DPO with the attached minicomputer around. The 202D and the 202R were introduced together with the P7001 in 1973 and the Model 7 Rack Cart was officially released in 1977.


Not all options were available through the whole lifecycle of the DPO. As an Example: 4k Core Memory was the default configuration in early production years and became an option in later years. Other options like the CP bus Interface got an update and a new part number.

Option Description Kit- or Partnumber Price in 1981
3 Electromagnetic Interference (EMI) Shielding 040-0671-00 +$185
9 Change line voltage to 230V/50Hz - No Charge
18 Change to 1k Semiconductor Memory 670-2981-00 -$1045
19 Change to 2k Semiconductor Memory 670-3035-00 -$760
20 Change to 4k Core Memory 672-0057-00 +$315
31 Add IEEE 488 Bus Interface 021-0206-00 +$2000
32 Add CP Bus Interface 021-0116-00,
021-0116-02 or
? Add Hardware Signal Average (HSA) Module 644-0092-00 or

Programming Examples

Various ways of data access

The following examples might help to understand the programming differences between 16- and 10-bit data access and high level information access. All three examples write the word "HELLO" to the Location D in Message Field 2 and instruct the Readout Interface to show this Message on the CRT. Descriptions of the Readout Interface Status Register and data format can be seen in the images above. There is also an overview of the P7001 Address Map.

Example A: 16 bit Memory or Register Access While the data bus of the P7001 is 16 bit wide, most of the stored data is only 10 bit wide. More importantly, bit 0 of the needed data word is not always aligned to bit 0 of the data bus. A very good example of this design is the data format of the Readout Interface. Bit 0 of the readout information starts at bit 5 on the data bus. To get or write the readout information we have to shift and crop or expand the data bits.

The ASCII code for the character "H" is 72. Converted to 16 bit binary and shifted 5 times to the left: 0000100100000000 or in octal notation: 004400. Our destination message field starts at memory location 3456 (octal: 6600). We can do the same calculations for the other readout characters. At the end we have to instruct the Readout Interface to display the message. For displaying Location D of Message field 2, we have to set the bits 6 and 14 of the Readout Interface Register. In binary notation: 0100000001000000 In octal notation: 040100 The register is located at memory address 7296 (octal: 16200)

The final program might look like:

	SEND ("ADR 3456", "OCT 004400") // 'H' -> ASCII 72 -> 0000100100000000 -> 004400
	SEND ("ADR 3457", "OCT 004240") // 'E' -> ASCII 69 -> 0000100010100000 -> 004240
	SEND ("ADR 3458", "OCT 004600") // 'L' -> ASCII 76 -> 0000100110000000 -> 004600
	SEND ("ADR 3459", "OCT 004600") // 'L' -> ASCII 76 -> 0000100110000000 -> 004600
	SEND ("ADR 3460", "OCT 004740") // 'O' -> ASCII 79 -> 0000100111100000 -> 004740
	SEND ("ADR 7296", "OCT 040100") // Show Message field 2 / Location D on CRT

Example B: 10 bit Memory Access Most of the time we're dealing with 10 bit data information. To make life easier, Tektronix implemented the "WRD" instruction set on the controller. This instruction set handles the data conversion between the ASCII data and the 16 bit universe of the P7001. The command also implements an auto-increment for the address data.

The new program looks like:

	SEND ("ADR 3456" , "WRD 72") //'H'
	SEND ("WRD 69") //E  -> the destination address is auto-incremented
	SEND ("WRD 76") //L
	SEND ("WRD 76") //L
	SEND ("WRD 79") //O
	SEND ("ADR 7296", "OCT 040100") // Show Messagefield 2 / Location D on CRT

Example C: High Level Instruction Set Finally, there is a high-level command implemented which sends the readout data in one line: SEND ("ADR 3456", "SCL HELLO ") // The last space is needed as terminator character. SEND ("ADR 7296", "OCT 040100") // Show Message field 2 / Location D on CRT

X/Y Mode

A description of the Display Generator Status Register and Data Format can be seen in the images above.

The Display Generator Status Register is located at memory location 7168 (octal: 16000). To enable the software-controlled X-Y Display and waveform "D", we have to set bit 13 and 6 in this register. In binary notation: 0010000001000000 In octal notation: 020100

To display a shape, we have to continuously move the beam around from point to point. The X/Y coordinates for the lower left point on the CRT is 7680/0 (octal: 17000/0), and for the upper right point 8191/1023 (octal: 17777/1777). We can also control the beam intensity of each movement between 0 (disabled) and 3 (full brightness). The Y-value and brightness level are encoded into the Display Generators Data Format and the result is sent to the desired X-Address of the Display Generator.

The resulting program in pseudo-code:

	SEND ("ADR 7168", "OCT 020100")			//enable X-Y Mode for Waveform "D"

	SEND ("ADR 7834", "OCT 063100")			//blank the beam and move it invisible to the start point of drawing

	Start loop					//write a T-shaped curve continuously in a loop at full intensity
		SEND ("ADR 8069", "OCT 063130")
		SEND ("ADR 8069", "OCT 054030")
		SEND ("ADR 7981", "OCT 054030")
		SEND ("ADR 7981", "OCT 014670")
		SEND ("ADR 7918", "OCT 014670")
		SEND ("ADR 7918", "OCT 054030")
		SEND ("ADR 7834", "OCT 054030")
		SEND ("ADR 7834", "OCT 063130")
	End loop

	SEND ("ADR 7168", "OCT 000100")			//disable X-Y Mode for Waveform "D"

Bugs & Errors

Design Flaw of the A/D Converter

The dynamic range of the sampled waveform is greater than the converted output of the A/D converter. Any sampled point which is left to the CRT viewing area will be added to memory location 0, and any point which is right to the CRT viewing area will be added to memory location 511. The end points (0 and 511) of the acquired waveform data should be considered invalid for measurement purposes. ServiceTekNotes Issue 25, Sep 1982 describes the problem and shows a possible solution.

Firmware Bug in GPIB interface

Affected Firmware versions: all

Due to an error in the firmware, pin 9 of U123 is always configured as an output pin. This pin is directly connected to an output of the line driver IC U321. To prevent damage to the PIA chip, it is recommended to remove the line driver U321. Since U321 is only needed for internal testing, it can be removed without any problems.

Catalogs & Advertising

Introduction March 1973

Field of Application

Appearance in Tektronix Magazines


Some Parts Used in the P7001

Part Part Number(s) Class Description Used in
155-0014-01 155-0014-00 155-0014-01 Monolithic integrated circuit A/D converter 7000 series readout system 7854 7934 7J20 7L5 P7001
155-0022-00 155-0022-00 155-0022-01 Monolithic integrated circuit analog multiplexer 147 148 149 335 468 1430 1441 1461 1900 1910 2220 2221 2230 5223 5403 5440 5441 5443 5444 5A38 7313 7403N 7503 7504 7514 7603 AN/USM-281C 7613 7623 7623A 7633 7704 R7704 7704A 7834 7844 7854 R7912 7912AD 7912HB 7904 R7903 7904A 7934 7A12 7A18 7A18A 7A18N 7B52 7B53N 7D10 7D11 7D12 NT-7000 P7001
155-0035-00 155-0035-00 155-0116-00 Monolithic integrated circuit quad op-amp 3110 3S7 3T7 492 492A 492AP 492P 494 494P 496 496P 4010 4011 4012 4013 7L5 7L12 7L13 7L14 7L18 7S11 7T11 7S12 S-6 1461 4602 P7001 613 653
155-0067-02 155-0067-00 155-0067-02 155-0067-03 Monolithic integrated circuit SMPS controller 7704A 7834 7844 7854 7904 R7903 7904 7904A 7934 R7912 7912AD 7912HB 7934 7104 R7103 308 434 485 690 P7001
Intel 2102 156-0291-00 Monolithic integrated circuit 1k×1 static RAM 833 DF1 DF2 P7001 Nicolet 526